(1) Field of the Invention
The present invention relates to a method for making integrated circuits on semiconductor substrates. The method is for forming interlevel dielectric (ILD) layers having improved gap filling between closely spaced conducting lines. In particular the method utilizes the removal of sidewall spacers on closely spaced FET gate electrodes after forming self-aligned lightly doped source/drain areas and source/drain contact areas, and before depositing an ILD layer.
(2) Description of the Prior Art
As the Ultra-Large Scale Integration (ULSI) circuit density increases and device features sizes become less than 0.25 micrometers, increasing numbers of patterned electrically conducting levels are required with decreasing spacings between conducting lines at each level to effectively wire up discrete semiconductor devices on semiconductor chips. In the more conventional method the different levels of electrical interconnections are separated by layers of insulating material. These interposed insulating layers have etched via holes which are used to connect one conducting level to the next. A typical insulating material is silicon oxide (SiO2). More recently, however, dielectrics having a low dielectric constant k have been used, for example, values less than 4.0 are typically used to reduce the RC constant and thereby improve circuit performance. However, as the device dimensions decrease and the packing density increases, it is necessary to reduce the spacings (gaps) between the conducting lines to effectively wire up the discrete devices on a silicon substrate. Unfortunately, one level of interconnections where this is a particular problem is at the first level of polysilicon interconnections used to make FET gate electrodes and some of the local interconnections. As the spacings between the gate electrodes decreases, it is also necessary to retain the thickness of the polysilicon lines to maintain a reasonably low line resistance (sheet resistance) to achieve a low RC constant. Unfortunately, this results in a very high aspect ratio (height to width) for the gap or space between the lines. This increased aspect ratio makes it difficult to fill the gaps when the next level of insulation is deposited without forming unwanted voids, as shown in FIG. 1. This problem is best understood with reference to FIG. 1, in which a gate oxide 12 is grown on device areas on the surface of a substrate 10. Closely spaced gate electrodes 14 are formed next by depositing a polysilicon layer which is patterned. Then lightly doped source/drain regions 16 are implanted adjacent to the gate electrodes 14 (self-aligned). Sidewall spacers 18 are formed on the gate electrodes and source/drain (S/D) contact regions 20 are implanted self-aligned to the sidewall spacers. To improve the conductivity of the gate electrodes and to provide good ohmic contact to the S/D contacts, a metal, such as cobalt (Co) is deposited and annealed to form a self-aligned silicide 22 on the gate electrodes 14 and on the contacts 20. In the current semiconductor technologies the spacings or gaps between gate electrodes are quite narrow, and to retain reasonable conductivity the height (thickness) of the gate electrodes cannot be significantly reduced. After forming the sidewall spacers the aspect ratio of the gaps G, (ratio of the height of the polysilicon to the width between the sidewall spacers) can be quite large, for example, greater than 5.0. When an interlevel dielectric (ILD) insulating layer 24 is deposited, voids V are inadvertently formed in the ILD layer in the gaps G1 between the gate electrodes due to the nature of the deposition process. Typically these voids extend along the gate electrodes and local interconnections and can lead to electrical shorts when via holes are etched in the ILD layer. Therefore, there is a strong need in the semiconductor industry to eliminate these voids during ILD deposition.
Several methods for forming closely spaced conducting lines for high-density circuits have been described. For example, U.S. Pat. No. 5,751,040 to Chen et al. describes a method for forming vertical FETs for ROM memory cells in which a source is formed in a trench, an FET channel is formed in the trench wall, and a drain on the surface which are self-aligned. This allows the inventors to double the density of the FETs. Sheng et al. in U.S. Pat. No. 4,994,404 use a disposable amorphous carbon sidewall spacer to self-align the source/drain contacts to the LDD. The amorphous carbon is then removed. Gardner et al. in U.S. Pat. No. 6,365,943 B1 describe a method for making two levels of FET devices to increase circuit density on the chip. U.S. Pat. No. 6,380,535 B1 to Wu et al. describe a method for making sidewall spacers on an FET gate electrode without damaging the substrate during etching. Pham et al., U.S. Pat. No. 6,455,373 B1, make flash memory (floating gate) FETs in which the sidewalls are of different thicknesses on the source and drain sides to reduce leakage currents, such ion charge and the like.